The present invention relates to variable frequency AC motors and more particularly to an apparatus for altering stator winding voltages to eliminate greater than twice overvoltage.
One type of commonly designed induction motor is a three phase motor having three Y-connected stator windings. In this type of motor, each stator winding is connected to an AC voltage source by a separate supply line, the source generating currents therein. Often, an adjustable speed drive (ASD) will be positioned between the voltage source and the motor to control motor speed.
Many ASD configurations include a pulse width modulated (PWM) inverter consisting of a plurality of switching devices and a controller for controlling the inverter. Referring to FIG. 1, an exemplary inverter 9 has six switches 12-17. The switches 12-17 are arranged in series pairs, each pair forming one of three inverter legs 39, 40, and 41. Referring to leg 39, by triggering switches 12, 13 ON and OFF in a repetitive sequence, leg 39 receives DC voltage 18 and provides high frequency voltage pulses to a motor terminal 31.
Referring to FIG. 2, an exemplary sequence of high frequency voltage pulses 60 that inverter 9 might provide to terminal 31 can be observed along with an exemplary low frequency alternating fundamental voltage 62 and related alternating current 69. By varying the widths of positive portions 63 of each high frequency pulse relative to the widths of negative portions 64 over a series of high frequency voltage pulses 60, a changing average voltage which alternates sinusoidally can be generated. The changing average voltage defines the low frequency alternating voltage 62 that drives the motor. The low frequency alternating volatage 62 in turn produces a low frequency alternating current 69 that lags the voltage by a phase angle .phi.. By triggering switches 12 and 13 in a regulated sequence inverter 9 can be used to control both the amplitude and frequency of volatage 62 that eventually reach the 10 stator windings.
Referring to FIG. 3(a), representative waveforms used to generate triggering signals for leg 39 may be observed. As well known in the art, a carrier waveform 67 is perfectly periodic and operates at what is known as the carrier frequency. A command voltage waveform 68 is sinusoidal, having a much greater period than carrier waveform 67.
Referring also to FIGS. 3(b) and 3(c), an upper signal 72 and a lower signal 74 that control the upper and lower switches 12, 13 respectively can be observed. The turn-on t.sub.u1, t.sub.u2 and turn-off t.sub.o1, t.sub.o2 trigger times of the upper and lower signals 72, 74 come from the intersections of the command waveform 68 and the carrier waveform 67.
When waveform 68 intersects carrier waveform 67 while carrier waveform 67 has a positive slope (i.e. during periods T.sub.p), upper signal 72 goes OFF and lower signal 74 goes ON. On the other hand, when waveform 68 intersects carrier waveform 67 while carrier waveform 67 has a negative slope (i.e. during periods T.sub.n), upper signal 72 goes ON and lower signal 74 goes OFF. Thus, by comparing carrier waveform 67 to command waveform 68, trigger times can be determined.
Referring to FIGS. 1 and 3(d), an ideal high frequency voltage pulse 60 resulting from upper and lower signals 72, 74 in FIGS. 3(b) and 3(c) that might be provided at terminal 31 can be observed. When upper signal 72 is ON and lower signal 74 is OFF, device 12 allows current to flow from high voltage rail 48 to motor terminal 31 thus producing the positive phase 78 of pulse 60 at motor terminal 31. Ideally, when upper signal 72 goes OFF and lower signal 74 goes ON, device 12 immediately turns OFF and device 13 immediately turns ON connecting motor terminal 31 and low voltage rail 49 producing the negative phase 80 of pulse 60 at motor terminal 31. Thus, ideal high frequency voltage pulse 60 is positive when upper signal 72 is ON and negative when lower signal 74 is ON.
The method by which waveform comparison is implemented depends on the type of hardware used to configure a controller. Controller hardware can generally be divided into two different types, analog and digital. Therefore, generally, there is an analog method for waveform comparison and a digital method for waveform comparison.
Referring to FIG. 4, a typical analog controller 300 includes a processor 302, a discretizer 304, a compare register 306 and a carrier generator 308. Processor 302 generates three sinusoidal analog command waveforms (one shown in FIG. 3(a)) which are provided to discretizer 304. Discretizer 304 (e.g., an ASIC) samples each command waveform 68 at a frequency much higher than the frequency of carrier waveform 67 and generates three discretized signals on lines 301, 303 and 309.
Referring also to FIG. 5, an exemplary discretized signal 305 corresponding to command waveform 68 is illustrated along with carrier waveform 67. Clearly, discretized signal 305 closely tracks waveform 68. The discretized signals are provided to register 306.
Referring still to FIGS. 4 and 5, generator 306 provides carrier signal 67 to register 306 on line 307. Register 306 compares discretized signal 305 to waveform 67 to generate upper switch trigger ON time .tau..sub.21 and OFF time .tau..sub.22. Because discretized signal 305 closely tracks waveform 68, times .tau..sub.21 and .tau..sub.22 closely approximate ON and OFF times t.sub.u1 and t.sub.o1, respectively, in FIG. 3(b).
Referring to FIG. 6, a typical digital controller 310 includes a processor 312, a trigger time register 314, a compare register 316 and a carrier count generator 318. Instead of comparing waveforms, controller 310 compares times. Processor 312 generates trigger times. The trigger times approximate turn ON and turn OFF times t.sub.u1, t.sub.o1 respectively. Instead of generating a triangle carrier waveform 67 like generator 308 (see FIG. 4), generator 318 provides a carrier count signal to register 316 which is indicative of waveform 67.
Referring again to FIG. 3(a), for the purpose of this explanation, a carrier period T.sub.c is the time between consecutive peak carrier waveform amplitude values A.sub.max. During a first half T.sub.n of each carrier period T.sub.c, the carrier count counts down from a maximum count value C.sub.max to a minimum count value C.sub.min. Similarly, during a second half T.sub.p of each carrier period T.sub.c, the count counts up from minimum count C.sub.min to maximum count C.sub.max. To simplify this explanation it will be assumed maximum count C.sub.max is 100 and minimum count C.sub.min is 0.
An example of how processor 312 operates to generate trigger times is instructive. Referring still to FIG. 3(a), in addition to waveforms 67 and 68, an amplitude signal 71 is also illustrated. Signal 71 is generated internally by processor 312. To generate signal 71, at the beginning of each carrier period T.sub.c processor 312 normalizes waveform 68 to the DC bus voltage V.sub.bus so that a waveform 68 amplitude A.sub.n is between +1/2 and -1/2. Processor 321 samples command waveform 68 and discretizes amplitude A.sub.n at the beginning of each carrier waveform period T.sub.c. In FIG. 3(a), at time .tau..sub.17 which is the beginning of period T.sub.c, amplitude A.sub.n is A.sub.1 and therefore signal 71 is set to amplitude A.sub.1 for the duration of period T.sub.c. At the end of period T.sub.c at time .tau..sub.18, amplitude A.sub.n is A.sub.2 and therefore signal 71 is set to amplitude A.sub.2 for the duration of the period following period T.sub.c. This process of discretizing waveform 68 to generate signal 71 at the beginning of each carrier period T.sub.c is continuous.
Just after amplitude A.sub.n is set at the beginning of each carrier period T.sub.c and prior to the next intersection between signal 71 and waveform 67, processor 312 determines an upper switch ON duty cycle DC according to the following equation: ##EQU1## For example, where A.sub.n is 0.25, duty cycle DC will be 75% (i.e., 0.25+0.50).
Next, processor 312 determines upper switch trigger times by multiplying duty cycle DC by the maximum carrier count C.sub.max. Assuming a 75% duty cycle DC, upper switch trigger times occur when the carrier count is 75 (i.e., 0.75*100). Thus, referring to FIGS. 3(a) and 3(e), at time .tau..sub.17, processor 312 identifies times .tau..sub.19 and .tau..sub.20 as the turn ON and turn OFF times of an associated upper switch. In the example, both of times .tau..sub.19 and .tau..sub.20 identify counts of 75, time .tau..sub.19 during period T.sub.n and time .tau..sub.20 during half period T.sub.p. Times .tau..sub.19 and .tau..sub.20 corresponding to waveform 68 are provided to register 314 which stores the times. Similarly, other trigger times corresponding to the other two command waveforms (not illustrated) are provided to register 314.
During period T.sub.c registers 316 also receives the carrier count signal for comparison. During first half period T.sub.n, as the count counts down from 100 (i.e., C.sub.max) to 0 (i.e., C.sub.min), the count reaches time .tau..sub.19 at 75 and generates an upper switch ON trigger signal. During second half period T.sub.p as the count counts up from 0 to 100, the count reaches time .tau..sub.20 at 75 and generates an upper switch OFF trigger signal. Thus, referring to FIG. 3(e), with a digital controller which compares trigger times to a carrier count and discretizes waveform amplitude A.sub.n only once per carrier cycle T.sub.c, resulting high frequency voltage 322 includes positive phases 323 which are carrier signal centered. In other words, during a first and a third segment T.sub.1 and T.sub.3, respectively, of period T.sub.c, voltage 322 is low, therebetween during a second segment T.sub.2, voltage 322 is high and segments T.sub.1 and T.sub.3 have identical durations.
Referring again to FIG. 1, Insulated Gate Bipolar Transistors (IGBTs) are the latest power semiconductor switches used in a PWM inverter 9. IGBTs have fast rise times and associated switching speeds (e.g. 50-400 ns) that are at least an order of magnitude faster than BJTs and other similar devices. At IGBT switching speeds, switching frequency and efficiency, and the quality of terminal voltages, are all appreciably improved. In addition, the faster switching speeds reduce harmonic heating of the motor winding as well as reduce audible motor lamination noise.
While IGBT PWMs are advantageous for all of the reasons identified above, when combined with certain switch modulating techniques (i.e. certain on/off switching sequences), IGBT fast dv/dt or rise times can reduce the useful life of motor components and/or drive to motor voltage supply lines. In particular, while most motors and supply lines are designed to withstand operation at rated line voltages for long periods and to withstand predictable overvoltage levels for short periods, in many cases, fast switch rise times causes overvoltages that exceed design levels.
For a long time the industry has recognized and configured control systems to deal with twice overvoltage (i.e. twice the PWM inverter DC power supply level) problems. As well known in the controls art, twice overvoltage levels are caused by various combinations of line voltage rise time and magnitude, imperfect matches between line-to-line supply cable and motor surge impedances, and cable length. Line voltage frequency and switch modulating techniques have little effect on twice overvoltage levels.
One common way to cope with twice overvoltage levels has been to reduce reflected voltage by terminating the cable supply lines at the motor terminals with a cable to motor surge impedance matching network. Resistor-Inductor-Capacitor or R-L-C filter networks mounted at the drive output are also used to change and reduce the slope of the voltage pulses (i.e. the turn on times) as they arrive. This network increases the cable distance where twice voltage in the motor terminals is developed to a length outside the application distance of interest. In addition, to reduce the possibility of damage from periodic twice overvoltage levels, most cable supply lines and motors are insulated to withstand periodic twice overvoltage levels. Thus, the industry has developed different system configurations for dealing with twice overvoltage.
Unfortunately, there is another potentially more damaging overvoltage problem that has not been satisfactorily dealt with. The second overvoltage problem is referred to herein as greater than twice overvoltage. Unlike twice overvoltage, greater than twice overvoltage is caused by faster IGBT switching frequencies and faster IGBT dv/dt rise times interacting with two different common switch modulating techniques, that result in overvoltage problems referred to as "double pulsing" and "polarity reversal".
Referring to FIG. 7, double pulsing will be described in the context of an IGBT inverter generated line-to-line voltage V.sub.i applied to a line cable and a resulting motor line-to-line terminal voltage V.sub.m. Initially, at time .tau..sub.1, the line is shown in a fully-charged condition (V.sub.i (.tau..sub.1)=V.sub.m (.tau..sub.1)=V.sub.DC). A transient motor voltage disturbance is initiated in FIG. 7 by discharging the line at the inverter output to zero voltage, starting at time .tau..sub.2, for approximately 4 .mu.sec. The pulse propagation delay between the inverter terminals and motor terminals is proportional to cable length and is approximately 1 .mu.sec for the assumed conditions. At time .tau..sub.3, 1 .mu.sec after time .tau..sub.2, a negative going V.sub.DC voltage has propagated to the motor terminals. In this example, a motor terminal reflection coefficient .left brkt-top..sub.m is nearly unity. Thus, the motor reflects the incoming negative voltage and forces the terminal voltage V.sub.m to approximately negative bus voltage: EQU V.sub.m (.tau..sub.3)=V.sub.m (.tau..sub.1)-V.sub.DC (1+.left brkt-top..sub.m).apprxeq.-V.sub.DC Eq. 2
A reflected wave (-V.sub.DC) travels from the motor to the inverter in 1 .mu.sec and is immediately reflected back toward the motor. Where an inverter reflection coefficient .left brkt-top..sub.i is approximately negative unity, a positive V.sub.DC pulse is reflected back toward the motor at time .tau..sub.4. Therefore, at time .tau..sub.4 the discharge at time .tau..sub.2 alone causes a voltage at the motor terminal such that: EQU V.sub.m (.tau..sub.4)=V.sub.m (.tau..sub.1)-V.sub.DC (1+.left brkt-top..sub.m)-V.sub.DC .left brkt-top..sub.i .left brkt-top..sub.m (1+.left brkt-top..sub.m).apprxeq.V.sub.DC Eq. 3
In addition, at time .tau..sub.4, with the motor potential approaching V.sub.DC due to the .tau..sub.2 discharge, the inverter pulse V.sub.i (.tau..sub.4) arrives and itself recharges the motor terminal voltage to V.sub.DC. Pulse V.sub.i (.tau..sub.4) is reflected by the motor and combines with V.sub.m (.tau..sub.4) to achieve a peak value of approximately three times the DC rail value: EQU V.sub.m (.tau..sub.4 +)=V.sub.m (.tau..sub.1)-V.sub.DC (1+.left brkt-top..sub.m)-V.sub.DC .left brkt-top..sub.i .left brkt-top..sub.m (1+.left brkt-top..sub.m)+V.sub.i (.tau..sub.4)(1+.left brkt-top..sub.m).apprxeq.3V.sub.DC Eq. 4
Referring to FIG. 8 polarity reversal will be described in the context of an IGBT inverter generated line-to-line voltage V.sub.il and a resulting motor line-to-line voltage V.sub.ml. Polarity reversal occurs when the firing signal of one supply line is transitioning into overmodulation while the firing signal of another supply line is simultaneously transitioning out of overmodulation. Overmodulation occurs when a reference signal magnitude is greater than the maximum carrier signal magnitude so that the on-time or off-time of a switch is equal to the duration of the carrier period. Polarity reversal is common in all types of PWM inverter control.
Initially, the inverter line-to-line voltage V.sub.il (.tau..sub.5) is zero volts. At time .tau..sub.6, the inverter voltage V.sub.il (.tau..sub.6) is increased to V.sub.DC and, after a short propagation period, a V.sub.DC pulse is received and reflected at the motor terminals thus generating a 2V.sub.DC pulse across associated motor lines. At time .tau..sub.7, the line-to-line voltage switches polarity (hence the term polarity reversal) so that the inverter voltage V.sub.il (.tau..sub.7) is equal to -V.sub.DC when the line-to-line motor voltage V.sub.ml (.tau..sub.7) has not yet dampened out to a DC value (i.e. may in fact be 2V.sub.DC). After a short propagation period, the -2V.sub.DC pulse reaches the motor, reflects, and combines with the inverter reflected pulse -V.sub.DC its reflected pulse and the positive voltage 2V.sub.DC on the motor. The combination generates an approximately -4V.sub.DC line-to-line motor voltage V.sub.ml (.tau..sub.8) at time .tau..sub.8.
In reality, the amplitude of overvoltages will often be less than described above due to a number of system variables including line AC resistance damping characteristics, DC power supply level, pulse dwell time, carrier frequency f.sub.c modulation techniques, and less than unity reflection coefficients (.left brkt-top..sub.m).
One solution to the double pulsing problem has been to increase the zero voltage dwell time between line-to-line inverter pulses. In other words, referring again to FIG. 7, the discharge time between pulses would be extended from the present 4 .mu.secs so that, prior to the second pulse V.sub.i (.tau..sub.4) reaching the motor terminals, the motor terminal voltage transient V.sub.m reaches a steady state DC value.
While increasing the zero voltage dwell time between line-to-line inverter pulses eliminates greater than twice overvoltage due to double pulsing, this solution can disadvantageously reduce the amplitude of the resulting fundamental low frequency terminal voltage where high carrier frequencies and overmodulation occurs. For example, referring to FIG. 9, a series of high frequency voltage pulses 5 at a motor terminal and a resulting fundamental low frequency terminal voltage 6 can be observed. In FIG. 9, a positive phase of the low frequency voltage begins at time .tau..sub.9 and ends at time .tau..sub.10.
To eliminate greater than twice over voltage, one pulse limiting scheme indiscriminately increases the duration of each off time period that is less than a minimum allowable off time. In FIG. 9, the off times of pulses during periods .zeta..sub.2 and .zeta..sub.3 are equal to associated carrier periods and therefore are greater than the maximum on time and thus would both be limited. In addition, in many cases greater than twice over voltage will occur prior to and just after overmodulation. Thus, referring still to FIG. 9, during periods .zeta..sub.1 and .zeta..sub.4 and periods just before period .zeta..sub.1 and just after period .zeta..sub.4, off times will also often be limited. Where the magnitude of the DC power supply is reduced substantially, the number of overmodulation carrier periods having limited on-times increases proportionally until, at some point, the reduced on-time noticeably affects the low frequency terminal voltage magnitude. In other words, maximum power output is substantially reduced through blind limitation of firing pulses during overmodulation.
While FIG. 9 is only exemplary, it can be seen that during the positive phase (i.e. .tau..sub.9 -.tau..sub.10), the four firing pulses that would normally occur during carrier periods .zeta..sub.1 -.zeta..sub.4 would likely all be limited to a maximum on-time. In addition, pulses during periods just before period .zeta..sub.1 and just after period .zeta..sub.4 may also be limited. In many cases, especially where the DC supply magnitude is minimal or reduced, the reduction in low frequency terminal voltage is unacceptable.
In addition to reducing the magnitude of the fundamental low frequency voltage 6, this solution does not address the polarity reversal problem.
Another solution to the greater than twice overvoltage problem is described in U.S. patent application Ser. No. 08/701,950 entitled METHOD AND APPARATUS FOR CONTROLLING VOLTAGE REFLECTIONS USING A MOTOR CONTROLLER which was filed on Aug. 23, 1996 and is commonly owned with this application. According to this solution a motor controller monitors switch trigger times during future carrier periods and modifies trigger times in a manner calculated to eliminate switching sequences which will yield greater than twice overvoltage. When the period between consecutive upper switch ON and OFF trigger times is less than the period required for a substantially steady state voltage level to be reached, trigger times are modified such that the period between the consecutive ON and OFF trigger times is increased. Where trigger times result in greater than twice overvoltage due to polarity reversal, the trigger times are altered to eliminate the possibility of greater than twice overvoltage.
The described method requires a processor which can (1) identify ON and OFF periods during future carrier periods, (2) compare ON and OFF period durations to a duration which is known to cause greater than twice overvoltage and (3) can then modify the ON and OFF periods when necessary to eliminate greater than twice overvoltage.
On one hand, as described above, digital processors identify ON and OFF trigger times during each carrier period and therefore can modify trigger times when necessary.
However, on the other hand, as described above, analog processors simply generate analog command signals for real time comparison to a carrier signal. Thus, analog processors are incapable of looking ahead to identify ON and OFF periods during future carrier periods as required. For this reason, analog processors cannot in and of themselves modify turn ON and turn OFF times.
In addition, it should also be noted that, even where a controller includes a digital processor, because most processors are not configured to facilitate large numbers of calculations in addition to typical calculations required to generate trigger times, many digital processors may not be able to implement the method described in the above referenced patent. This is particularly true of inexpensive and relatively simple processors.
Therefore, it would be advantageous to have an apparatus for use with a PWM controller which includes an analog processor which can eliminate greater than twice overvoltage. In addition, it would be advantageous to have an apparatus for use with a PWM controller which includes a digital processor which can eliminate greater than twice overvoltage without requiring the processor to perform excessive calculations.